1. Field of the Invention
The present invention relates to a delay-locked loop (DLL) circuit, and more particularly to a delay-locked loop (DLL) circuit capable of achieving a stable lock state over a wide range of delay time.
2. Description of the Related Art
A delay-locked loop (DLL) circuit is a circuit that can output a periodic signal with the same period as an input clock signal, and with a delay equal to the period of the input clock signal.
FIG. 1 is a block diagram illustrating a conventional delay-locked loop circuit.
Referring to FIG. 1, the delay-locked loop circuit includes a phase frequency detector (hereinafter, referred to as PFD) 10, a charge pump circuit 20, a loop filter 30 and a voltage controlled delay line (hereinafter, referred to as VCDL) 40. The PFD 10 receives an input clock signal FIN and a feedback signal FFEED, and detects phase difference between the two signals to generate an up signal UP and a down signal DOWN. The charge pump 20 receives the up signal UP and the down signal DOWN to generate a current signal that varies with logic states of the up signal UP and the down signal DOWN. The loop filter 30 receives the current signal from the charge pump circuit 20 and filters the current signal through the low-pass filtering to generate a dc voltage signal VFILT. The VCDL 40 receives the input clock signal FIN and the dc voltage signal VFILT and delays the input clock signal FIN by predetermined time in response to the dc voltage signal VFILT. The delayed signal from the VCDL becomes an output signal DLLO and the feedback signal FFEED.
FIGS. 2A through 2D are timing diagrams illustrating locked states according to conditions of delay times in the conventional delay-locked loop circuit shown in FIG. 1. FIG. 2A represents a locked state when Tin/2<Td<2×Tin. FIG. 2B shows a locked state when Td≧2×Tin and FIG. 2C shows a locked state when Td≦Tin/2, both indicating a harmonic lock. In FIG. 2D, the PFD is used instead of a phase detector (hereinafter, referred to as PD). When an initial state of the PFD is distorted, the PFD can output the up signal UP notwithstanding that the down signal DOWN has to be outputted, so that the VCDL may output a distorted output signal, not a restored signal. The lock state as in FIG. 2D is referred to as a dead lock. The harmonic lock and the dead lock should be prevented in order to implement a DLL having a wide lock range.